Design and Specifications#
If you want to know how BeagleBadge is designed and the detailed specifications, then this chapter is for you. We are going to provide you a short and crisp overview followed by discussing each hardware design element in detail.
Note
The component details in this chapter are taken from the BeagleBadge v1.0 bill of
materials and schematic published in the
BeagleBadge repository
(BeagleBadge_V1.0_SCH_260728.pdf and BeagleBadge_BOM.csv). The upstream README
notes that specifications are based on the current bill of materials and are subject to
change while the design is being finalized.
Download the schematic#
The complete 25-sheet schematic is available as a single PDF:
BeagleBadge_V1.0_SCH_260728.pdf- BeagleBadge v1.0 schematic, 25 sheets, dated 28 July 2026.
Every sheet of that PDF appears somewhere in this chapter, embedded next to the section that explains it. The table of contents sheet below lists them all.
Sheet 01 carries no circuitry. The left half is the schematic’s own table of
contents, and the right half is the revision history of BeagleBadge, from the
initial Rev A of 14 October 2025 through to V1.0 of 28 July 2026. It is the
quickest way to see what changed between board revisions and why, including the
decisions to leave eMMC unpopulated, to merge the boot and select functions onto one
button, and to move the “Other GPIOs” pins to 1.8 V.
Tip
The schematic sheets in this chapter are interactive: click a highlighted block
to read about it, use the toolbar to zoom, and press F for a full-screen
walk through every annotated sheet. In the PDF build the same highlights are
drawn on the vector page and link to the descriptions below it.
Block Diagram and Overview#
How the SoC, memories, radios, display and expansion connectors relate to one another. Worth reading before any individual sheet.
Power Tree#
Every rail on the board, from the USB-C and battery inputs down to the SoC supplies, with the regulator that generates each one and the current it can deliver.
SPI & I2C Tree#
Which device sits on which I2C bus, and how the SPI chip selects are allocated. Check here for address clashes before adding a QWIIC, Grove or mikroBUS device.
System on Chip (SoC)#
BeagleBadge is built around the Texas Instruments
AM62L32 (AM62L32BOGHAANBR), a low-power
member of the K3 Sitara family targeted at IoT, human-machine-interface (HMI) and
general-purpose applications where battery life matters as much as compute.
Some of the main characteristics of the device are:
Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem running at up to 1.25GHz, with 32KB L1 instruction and data caches per core and a shared 256KB L2 cache
160KB of shared on-chip SRAM (OCSRAM)
16-bit LPDDR4/DDR4 memory interface running at up to 1600MT/s
Single display output supporting up to 1920x1080 at 60fps over MIPI DSI (4-lane D-PHY) or DPI (24-bit RGB LVCMOS)
Two USB 2.0 dual-role device subsystems
eMMC (HS200), SD/SDIO (UHS-I) and OSPI/QSPI storage interfaces
Eight UARTs, four SPI, five I2C and three McASP audio ports
One 12-bit ADC with four inputs at 2MSPS
Multi-voltage configurable GPIO banks (1.8V/3.3V)
Deep low-power modes including Standby, DeepSleep, RTC+IO+DDR and RTC-only
373-pin FCCSP package, 11.9mm x 11.9mm, built on a 16nm process
Tip
The AM62L32 has no separate Cortex-R5F MCU island and no PRU subsystem. If you are coming from BeagleBone class hardware, plan for the Cortex-A53 cores plus the on-chip peripherals to do all the work.
Clocks, wake-up and reset#
BeagleBadge runs from two crystals: X1, a 25MHz 10ppm part on WKUP_OSC0, is the
main system reference, and X2, a 32.768kHz 20ppm part on LFOSC0, keeps the
real-time clock running while the rest of the SoC is powered down.
Reset arrives at the SoC on three pins: PORZ is the cold power-on reset from the
PMIC, RESETZ the warm reset from the RESET button, and RESETSTATZ a status output
that the rest of the board uses to hold peripherals off until the SoC is out of reset.
X1 (25MHz) and X2 (32.768kHz), the wake-up and RTC domains, and the three
reset entry points into the SoC.
The wake-up domain of the AM62L32, the part of the SoC that stays alive in low
power modes. It carries WKUP_I2C0 to the PMIC, the WKUP_UART0 pins (reused here
as GPIO on the expansion header), WKUP_CLKOUT0 and the MDIO0 pair. X1, a
25 MHz 10 ppm crystal, is the main system oscillator on WKUP_OSC0_XI /
WKUP_OSC0_XO.
The always-on real-time-clock domain. X2 is a 32.768 kHz, 9 pF, 20 ppm crystal on
LFOSC0_XI / LFOSC0_XO and keeps time while the rest of the SoC is powered down.
RTC_PORZ is the RTC power-on reset from the PMIC, PMIC_LPM_EN0 selects the low
power mode, and EXT_WAKEUP0 / EXT_WAKEUP1 are the two external wake inputs -
EXT_WAKEUP0 is also brought out to pin 12 of the SOICbite connector.
Reset entry points on the SoC. PORZ is the cold power-on reset from the PMIC,
RESETZ the warm reset asserted by the RESET button and the reset combiner on sheet
07, and RESETSTATZ the status output the board uses to hold peripherals off until
the SoC is out of reset. It fans out to ten other sheets. EXTINTN is the external
interrupt input. Revision V1.0 removed U60 so that the USB hub is now reset
directly from a GPIO instead.
Peripheral interfaces#
This sheet is where most of the SoC’s pin budget is decided. It shows the four ADC inputs, the MIPI DSI PHY, the MCASP audio pins reused as PWM and GPIO, the I2C, UART and SPI buses, and both RGMII Ethernet ports, which carry no PHY on this board and are instead brought out to the GPIO expansion header as 1.8V GPIO.
The SoC 12-bit ADC, four inputs at 2 MSPS on the VDDA_ADC rail:
ADC0_AIN0(V20): battery voltage sense, sheet 05ADC0_AIN1(V22): mikroBUSANpin, sheet 22ADC0_AIN2(V23): ambient light sensor output, sheet 21ADC0_AIN3(V21): brought out to the GPIO expansion header, sheet 24
All four are 1.8 V inputs. See Sensors.
The MCASP0 audio serialiser: four data lines AXR0-AXR3 plus transmit and
receive clock and frame sync. BeagleBadge fits no audio codec, so these pins are used
as 3.3 V GPIO and PWM instead: GPIO0_81, GPIO0_82 and GPIO0_83 drive the
RGB LED and the buzzer on sheet 21, and GPIO0_84 goes to the mikroBUS socket.
The MIPI DSI transmitter: a clock pair and four data lanes on D-PHY, plus
DSI0_TXRCALIB with its R146 (499 ohm 1%) calibration resistor. The pairs run to
the 22-pin FPC connector on sheet 24. VDDA_1P8_DSI and VDDA_CORE_DSI supply the
PHY. See MIPI DSI.
Both RGMII ports of the AM62L32. BeagleBadge fits no Ethernet PHY: all 24
RGMII pins and the MDIO0 pair are repurposed as 1.8 V GPIO and routed to the
expansion header on sheet 24. This is why the header silkscreen carries SoC ball names
such as Y8, AA6, W8 and AC10 rather than GPIO numbers.
See GPIO expansion header.
The general-purpose serial buses, all in the 3.3 V VDDSHV1 bank:
I2C0: PMIC, fuel gauge, board-ID EEPROM and the IMUI2C1: QWIIC connector 1, the mikroBUS socket, the ePaper touch option and the Grove connectorI2C2: QWIIC connector 2 only, so a module with a fixed address can be used on both QWIIC connectors at onceUART0: the serial debug console, via the CP2102N bridge on sheet 17UART1: the Wi-Fi/BLE module on sheet 18UART5: the mikroBUS socketSPI0: the ePaper panel on sheet 23MCAN0: not used on this board
GPIO0_95 (Right) and GPIO0_104 (BACK) are joystick and button inputs.
Boot Modes#
The AM62L32 reads its 16 SYS_BOOTMODE strap pins at power-on and takes a primary and
a backup boot device from them. On BeagleBadge the straps are set by resistors, except for
the bits that the SELECT/BOOT button overrides.
At power-on |
Primary boot |
Backup boot |
Used for |
|---|---|---|---|
SELECT released |
OSPI NOR flash |
UART |
Normal start-up from the boot chain in flash |
SELECT held |
microSD card |
USB DFU |
Booting an image from a card |
If the primary device holds no valid boot image, the ROM moves on to the backup device. With SELECT held, a card that is missing or not bootable leaves the board waiting as a USB DFU device rather than falling back to the OSPI flash.
Note
The straps are read only at power-on. RESET is a warm reset and keeps the current boot device, so to change it, switch the board off and on again with the Power button or by reconnecting power.
What the OSPI flash is for#
The 32MB OSPI flash holds the boot chain, not a Linux root filesystem. The AM62L32 has no
Cortex-R5 core to start the SoC, so its ROM boots in two phases: the first loads
tiboot3.bin (TF-A BL1, which brings up the LPDDR4), the second loads tispl.bin
(TF-A BL31 and U-Boot SPL), which then loads u-boot.img. Together these take a few
megabytes, leaving most of the flash free. See TI’s
AM62L U-Boot boot flow
for the details.
With the boot chain in OSPI:
U-Boot finds an operating system on the microSD card by itself, so a card boots without holding SELECT.
U-Boot can also boot from USB storage or over the network.
A Zephyr application, typically a few kilobytes to a few megabytes, can live in the flash and start with no card at all. See Running Zephyr.
The 16 BMODE strap resistors, the bus switches that override them, and the boot
mode truth tables printed on the sheet.
U73/U74 (SN74CBTLV3257) are 4:1 bus switches that disconnect SPI1 and
UART4 from their peripherals while the SoC is in reset (RESETSTATz low), so the
strap resistors on those shared pins are sampled cleanly at boot.
Part H of the AM62L symbol: the GPMC0 bank whose pins double as
SYS_BOOTMODE[15:0] straps and, after boot, as joystick, button, SPI1/SPI3 and
UART4 GPIOs (3.3 V domain).
Each SYS_BOOTMODEx line has a 10 kΩ pull-up and 100 kΩ pull-down footprint. The
populated set selects the default configuration. D6/D52/D49 let the
Select/BOOT button override bits 3, 6 and 10: released → OSPI CS0 boot, UART
backup. Pressed → SD-card FS boot, USB DFU backup. See Boot Modes.
Reference tables printed on the sheet: the 16-bit SYS_BOOTMODE word for
OSPI → UART vs SD card → USB, and the PLL / primary /
backup boot decoding for the button-released and button-pressed cases.
U44 gates SYS_BOOTMODE6 and U72 (SN74LVC1G17) turns Joystick_Press
or Select into EXT_WAKEUP0/1V8, either button wakes the system from sleep.
Power Management#
BeagleBadge is designed to run from a single-cell lithium battery or from USB Type-C, with automatic switchover between the two and battery capacity reporting over I2C. To fully understand the power tree, see Power Tree.
The Type-C input and its protection, the 3.3V main buck, the charger with its power-path control, and the fuel gauge that reports state of charge over I2C.
The Type-C receptacle J1 is wired for 5 V power and USB 2.0 data only (no
alternate modes, no Power Delivery). R4/R5 (5.1 kΩ) on CC1/CC2 advertise a
UFP sink so a Type-C source will supply 5 V. U1 (TVS0500DRVR) clamps surges on
TYPEC_5V_IN, L2 is a 90 Ω common-mode choke on the data pair and D1/D2
add ESD protection. The data pair goes to the USB hub upstream port
(see USB).
U2 (TPS62A06DRLR, 6 A synchronous buck) generates VCC_3V3_MAIN, the
always-on rail feeding the PMIC, load switches and the rest of the board. The feedback
divider R3/R6 (453 kΩ / 100 kΩ) sets Vout = 0.6 V × (1 + 453/100)
= 3.318 V. VCC_3V3_MAIN_EN gates the converter and the power-good output goes
to the RTC-mode logic on sheet 6. See Rails, converters and load switches.
U41 (BQ24070RHLR) is a single-cell Li-Ion linear charger with dynamic
power-path management: the system runs from VSYS_OUT while the battery charges,
and switches to the battery seamlessly when USB-C is removed. In v1.0 R341 was
changed to 2.4 kΩ, reducing the fast-charge current to about 430 mA, and the
timer resistor sets a 6 h safety timer. STAT1/STAT2 drive the two green
charge-status LEDs (LED181, LED191) and the table on the sheet lists the
LED states. See Battery charging and power path.
U43 (BQ27220YZFR) measures charge flowing through the 10 mΩ sense resistor
R501 and reports state of charge over I2C0 (3.3 V). GPOUT is routed to
M21/GPIO0_40 for battery-low interrupts. The gauge is powered from VDD_Fuel,
derived directly from VBAT so it keeps counting while the SoC sleeps.
J2 (ST-BC-Y3103) has three spring contacts for a Nokia BL-5C form-factor cell,
held to the board by two support legs. R639 was changed to an NTC in v1.0 so the charger suspends charging above
about 45 °C. R638/R640 scale the thermistor into the charger’s TS window.
Keep R638, R639 and R640 close to J2.
R311/R310 (180 kΩ / 100 kΩ) divide 0-5 V on VBAT down to the 0-1.8 V range
of ADC0_AIN0. The divider is switched by U58 (TPS22916) and enabled from
RESETSTATz so it draws no battery current until the SoC is out of reset.
C386 should be placed next to the AM62L ADC pin.
PMIC#
The main rails for the SoC and DDR are generated by a Texas Instruments
TPS6521401 (TPS6521401VAFR) power management
IC in a QFN-24 package, which integrates three DC/DC converters and two LDOs.
It runs from VCC_3V3_MAIN, the 3.3V rail generated by the U2 buck converter, and
uses TI’s default configuration for the AM62L, described in the
TPS6521401 technical reference manual.
Output |
Rail |
Supplies |
|---|---|---|
BUCK1 |
|
SoC core |
BUCK2 |
|
SoC 1.8V and RTC I/O, OSPI flash, LPDDR4 |
BUCK3 |
|
LPDDR4 |
LDO1 |
|
SoC 1.8V analog supplies |
LDO2 |
|
SoC RTC core |
At power-up the PMIC brings the rails up in this order:
GPIOenables theVDD_3V3load switch.BUCK2, LDO1 and LDO2.
BUCK3, and
GPOsignals RTC power-good toRTC_PORz.BUCK1.
nRSTOUTreleases the SoC from reset, about 19ms after the PMIC is enabled.
In standby, which is the RTC + IO + DDR low power mode, BUCK1 and LDO1 turn off and
nRSTOUT holds the SoC in reset. The other rails stay on so the LPDDR4 keeps its
contents. See Low power modes.
The TPS6521401 PMIC and the load switches and LDOs derived from it. Revision V1.0
reworked this sheet so that the 3.3V and 1.8V hub rails are powered only while
Type-C is connected.
U11 (TPS6521401VAFR) produces the SoC core rails from VCC_3V3_MAIN:
Buck1 (2 A) →
VDD_CORE(0.75 V)Buck2 (1 A) →
VDD_1V8Buck3 (1 A) →
VDD_LPDDR4(1.1 V)LDO1 (0.3 A) →
VDDA_1V8, LDO2 (0.5 A) →PMIC_VDD_RTC
The PMIC is controlled over WKUP_I2C0 and its nRSTOUT/nINT outputs go to
the SoC reset and wake-up domain. See PMIC.
U59 (SN74LVC1G17) buffers PORz_INPUT/1V8 into PMIC_RSTOUTn/1V8 so the
system can be reset either by the PMIC nRSTOUT or by the external reset input
(RESET button / SOICbite). The pull-ups R47, R54 and R625 reference the
signals to their respective 1.8 V and 3.3 V domains.
U5 (TPS22965DSGR, 6 A, 16 mΩ) gates VDD_3V3 from VCC_3V3_MAIN. It is
enabled by VDD_3V3_EN from the PMIC GPIO so that the peripheral 3.3 V domain is
sequenced after the core rails. C22 is DNI per the v0.3 change list.
U4 (TLV75801PDBVR, 500 mA adjustable LDO) creates USB_HUB_1V1 for the
TUSB4020B core. R22/R24 (100 kΩ / 100 kΩ) set 0.55 V × 2 = 1.1 V. The LDO is
enabled from USB_HUB_3V3 so both hub rails follow the Type-C presence.
U88 (TLV75801PDBVR) regulates TYPEC_5V_IN to USB_HUB_3V3 with
R648/R649 (100 kΩ / 20 kΩ) → 0.55 V × 6 = 3.3 V. Because its input is the
Type-C 5 V rail, the hub is only powered while a USB-C cable is connected. On
battery the hub and its 1.1 V LDO are off (design note on the sheet, added in v1.0).
Blue 0603 LED D3 with 4.7 kΩ series resistor R14 indicates that the switched
VDD_3V3 rail is up, i.e. the board has finished power sequencing.
Battery charging and power path#
Function |
Device |
Notes |
|---|---|---|
Charger and power path |
BQ24070 ( |
Single-cell Li-Ion/Li-Po linear charger with dynamic power-path management, so the board can run from USB while the battery charges |
Fuel gauge |
BQ27220 ( |
I2C battery fuel gauge for Li-Ion and Li-Polymer cells, reports state of charge to software |
Battery connector |
|
Three spring contacts for a Nokia BL-5C form-factor cell, held to the board by two support legs |
Revision V1.0 set the charge current with R341 (2.4K) to 430mA, and changed
R639 to an NTC thermistor so that charging stops at 45 degrees C. At 430mA a
typical 1000mAh BL-5C cell takes roughly three hours to charge.
Todo
Add the J2 contact order and the charger’s input current limit, from
schematic sheet 5.
Rails, converters and load switches#
Beyond the PMIC, discrete converters generate the main 3.3V input and the 5V and USB hub rails.
Part |
Output |
Notes |
|---|---|---|
|
|
Always on, feeds the PMIC and |
|
|
Type-A port, and the mikroBUS 5V pin limited to 0.1A |
|
|
From USB-C 5V, so on only while USB-C is connected |
|
|
Follows |
Load switches split the 3.3V supply into domains that can be turned off independently.
The ePaper panel and the QWIIC, Grove and mikroBUS 3.3V pins have no switch of their own.
They are on VDD_3V3.
Rail (switch) |
Enabled by |
Feeds |
|---|---|---|
|
PMIC |
SoC 3.3V I/O, ePaper, QWIIC, Grove, mikroBUS 3.3V, and the switches below |
|
SoC GPIO, gated by |
microSD card |
|
|
BM3301 Wi-Fi and Bluetooth module |
|
|
IMU, light sensor, RGB LED, 7-segment digits, GPIO expansion header pin 16 |
Battery sense ( |
|
Battery voltage divider on |
|
|
Type-A port VBUS |
SoC supply rails and decoupling#
The AM62L32 brings its supplies out on a large number of balls grouped into rails:
VDD_CORE for core logic, VDDS_DDR for the memory interface, the
VDDSHV0-VDDSHV4 multi-voltage I/O banks that allow 1.8V and 3.3V pin groups on
the same device, and separate analogue rails for the USB, DSI, ADC and PLL blocks.
Supply and ground balls grouped by rail. VPP is the efuse programming supply and
reaches 1.8V only through a header left unpopulated in production.
Every supply ball of the AM62L32 grouped by rail, showing which of the board rails
feeds each one. VDD_CORE (14 balls) is the core logic supply, VDDS_DDR the
LPDDR4 interface supply, and the VDDSHV0-VDDSHV4 banks are the multi-voltage
I/O domains that make the 1.8 V and 3.3 V pin groups possible. Analogue rails
(VDDA_1P8_USB, VDDA_3P3_USB, VDDA_CORE_USB, VDDA_1P8_DSI,
VDDA_CORE_DSI, VDDA_ADC, VDDA_PLL0/1) are broken out separately so each can
be filtered on its own. VPP is the one-time-programmable efuse supply and is tied
to 1.8 V through J16, a header left unpopulated on production boards.
The ground return for the SoC. The AM62L32 brings VSS out on roughly a hundred
balls spread across the 373-ball array, all tied to the board ground plane. The dense
ball count is a thermal and return-path requirement, not an electrical one: it keeps
the impedance of the return low under the DDR and USB interfaces.
Bulk and reservoir capacitance for the SoC internal regulators. CAP_VDDS_MMC0,
CAP_VDDS_MMC1, CAP_VDDS_MMC2, CAP_VDDS_GPMC, CAP_VDDS_GENERAL1 and
CAP_VDDSHV_MMC are not supply inputs: they are the external capacitors the SoC’s
on-die LDOs need to stay stable. They must sit close to their balls.
Decoupling for every SoC supply ball. The repeated layout note, one 0.1uF capacitor next to each pin, is the constraint that drives much of the board’s bottom-side component placement.
High-frequency decoupling for the SoC supply rails. Every supply ball gets its own
0.1 uF capacitor, as the repeated layout note on the sheet requires, backed by bulk
4.7 uF and 10 uF parts per rail. The EMIFIL three-terminal feedthrough capacitors
(C56-C62, C80-C84) are used where a plain two-terminal part would not
have enough self-resonant bandwidth.
Decoupling for the VDD_LPDDR4 rail feeding the SoC side of the memory interface.
LPDDR4 switching current is both large and fast, so this rail gets its own capacitor
bank rather than sharing with the core supply. See 256MB LPDDR4.
Decoupling for the remaining board rails at the SoC: VDD_3V3, VDD_3V3_SD,
VDD_1V8, VDDA_1V8, VDDSHV_SD_IO and the RTC pair SoC_VDD_RTC /
SoC_VDDS_RTC_1V8. FB1 (26 ohm, 6 A ferrite bead) isolates the analogue 1.8 V
rail from switching noise on the digital one.
Low power modes#
BeagleBadge is a battery-powered design, so the schematic provides for more than one
sleep depth. Revision V1.0 settled on RTC ONLY + IO + DDR as the final power mode
and removed the parts that the deeper RTC ONLY mode would have needed.
The two sleep depths the design provides for, and which components each one needs. Only the shallower of the two is populated.
U6, a TPS74501PDRVR LDO for the VDDS_RTC_1V8 rail (up to 0.5 A), enabled by
VDDS_RTC_1V8_EN. Not populated: it is only needed for RTC-only mode, and in the
populated RTC + IO + DDR configuration the PMIC supplies this rail.
U39, a TPS74501PDRVR LDO for the 0.75 V VDD_RTC rail (up to 0.5 A), enabled by
VDD_RTC_EN. Not populated, for the same reason as U6 beside it.
Selects which low-power mode the board supports. The sheet offers two:
RTC + IO + DDR: the default, and how the board ships. The components in the two supply blocks on this sheet are left unpopulated and the PMIC suppliesVDD_RTCandVDDS_RTC_1V8directly.RTC ONLY: the deepest mode. It requiresR41,R42,R45,R591,R596,R597,U6,U8,U10andU39to be populated,PMIC_LPM_EN0/1V8routed toPMIC_EN, andPMIC_STBYpulled up to 3.3 V.
Revision V1.0 settled on RTC ONLY + IO + DDR as the final power mode and removed
U6, U8, U10 and U39 from the build.
Memory, Media and Storage#
256MB LPDDR4#
BeagleBadge v1.0 has 256MB of system memory on a 16-bit bus. It comes from a single
ISSI IS43LQ16128A-062BLI LPDDR4 device in a 200-ball FBGA package, a 2Gb part
organised as 128M x 16.
Important
Some retail listings describe this as “2GB LPDDR4”. That is a unit error: 2 gigabit is 256 megabytes. The upstream BeagleBadge README, the Zephyr board documentation and the bill of materials all agree on 256MB.
The 2Gb device and the 16-bit SoC interface, with the 240 ohm ZQ calibration references and the routing impedance targets noted on the sheet.
U29, the IS43LQ16128A-062BLI LPDDR4 device in a 200-ball TFBGA. It provides 256 MB of
system memory on a 16-bit bus at up to 1600 MT/s, from a 2 Gb part organised as 128M x 16. Note the large number of NC and DNU balls: the footprint is the
standard LPDDR4 package, and a wider or denser device could drop into it.
See 256MB LPDDR4.
The SoC side of the memory bus: a 16-bit LPDDR4 interface with DDR0_DQ0-DQ15,
two data strobe pairs, two data masks, a 14-bit address bus, bank and command signals.
R104 and R106 (240 ohm 1%) are the ZQ calibration references and R105
(2.2 k) the DDR0_CAL0 reference. See 256MB LPDDR4.
Supply balls of the LPDDR4 device. LPDDR4 needs three separate rails: VDD1
(1.8 V) for the internal regulator, VDD2 (1.1 V) for the core array and VDDQ
(1.1 V) for the I/O drivers. VDD2_LPDDR4_1V1 and VDDQ_LPDDR4_1V1 come from the
PMIC. VDD1 shares the board VDD_1V8 rail.
Decoupling for the memory device, placed on the underside directly beneath the ball
field. The bank is mostly 10 nF 0201 parts so that each can sit as close to its ball as
possible, with 10 uF and 100 nF bulk parts per rail. The silkscreen marking for this
block is LPDDR4, and the impedance annotations on the sheet (80E, 66E) are
the routing targets for the data and command/address groups.
Storage#
Type |
Device |
Capacity |
|---|---|---|
OSPI NOR flash |
ISSI |
256Mb (32MB), FBGA-24 |
EEPROM |
FMD |
32Kb, I2C, SOT23-5 |
eMMC |
Footprint only |
Not populated on |
Removable |
|
microSD socket, 9-pin |
The EEPROM sits on I2C0 and follows the BeagleBoard.org convention of holding the
board identity, so software can detect which board it is running on. It is
write-protected by a pull-up on WP. Pull test point TP16 low to write it.
Todo
Add the EEPROM’s I2C address and the data format written at manufacturing, in the style of the AI-64 Expansion EEPROM section.
OSPI NOR flash#
The 256Mb device on its 1.8V octal bus, and the AND gate that holds it in reset until the SoC is out of reset.
The SoC octal SPI controller: OSPI0_CLK, eight data lines OSPI0_D0-D7, four
chip selects, the OSPI0_DQS read strobe and OSPI0_LBCLKO loopback clock. The
bus runs at 1.8 V from the VDDS1 bank. Only CSN0 is used, for the NOR flash
beside it.
U34, an ISSI IS25WX256-JHLE octal NOR flash in a 24-ball FBGA: 256 Mb
(32 MB), 1.8 V. It is the only non-removable boot medium on the board and holds
the boot chain. See What the OSPI flash is for.
U69 (SN74LVC1G08 AND gate) combines the SoC GPIO_OSPI_NOR_RSTn with the
board-wide RESETSTATz so the flash is held in reset until the SoC itself is out of
reset. Without this the flash could be mid-transaction when the SoC restarts. The
layout note asks for R526 to be placed close to the SoC.
microSD#
All three SoC MMC controllers appear on this sheet: MMC0 goes to the optional eMMC
footprint, MMC1 to the microSD socket, and MMC2 to the Wi-Fi module’s SDIO
interface.
All three SoC MMC controllers on one sheet. MMC0 (8-bit) is wired to the optional
eMMC footprint on sheet 25, MMC1 (4-bit, with card detect) to the microSD socket
here, and MMC2 to the Wi-Fi module’s SDIO interface on sheet 18. The
VDDSHV2-VDDSHV4 banks let each run at its own voltage.
J3 (ST-TF-003J, 9-pin push-push holder) on MMC1, with SD_MMC1_D0-D3,
CMD, CLK and the SD_MMC1_CD/3V3 card-detect line. D10-D16
(TPD1E1B04) provide ESD protection on every exposed contact and FB2 filters the
card supply. This is the removable boot medium. See Storage.
U17 (TPS22918DBVR load switch) gates VDD_3V3_SD to the card so software can
power-cycle it, which is how an SD card is recovered from a hung state.
U18 (SN74LVC1G08) gates the enable with RESETSTATz so the card stays
unpowered until the SoC is out of reset. VDDSHV_SD_IO follows the card rail so the
I/O bank tracks whatever voltage the card is running at, which is what allows both
3.3 V and 1.8 V UHS-I signalling.
eMMC footprint#
The SoC MMC0 bus is routed to a footprint for a 4GB eMMC device. No eMMC is fitted on
v1.0.
The footprint and its support components, all marked DNP on v1.0.
U15, a 4 GB EMMC04G-MT32-01G10 footprint in a 153-ball BGA on the SoC
MMC0 bus. It is not populated on v1.0, and the supporting parts
R110-R118 and U68 are DNP with it. See eMMC footprint.
Wireless Connectivity#
Wi-Fi and Bluetooth#
Wi-Fi and Bluetooth are provided by a BeagleBoard.org BeagleMod BM3301-1216, a 12 x 16mm
solder-down module in the
M.2 1216 LGA form factor, built on its
own 4-layer PCB and fitted as a sub-assembly. The module carries a Texas Instruments
CC3301ENJARSBR companion IC, a 40MHz reference crystal, a 2400-2500MHz band-pass
filter, a 1.8V LDO and an RF shield.
Wi-Fi uses the SoC MMC2 SDIO interface and Bluetooth uses UART1. The module’s
3.3V and 1.8V supplies both pass through load switches that are off by default, so the
radio stays powered down until software drives AB9/GPIO0_75 high. See
Rails, converters and load switches.
Parameter |
Value |
|---|---|
Wireless IC |
TI CC3301 SimpleLink companion IC |
Wi-Fi |
802.11ax (Wi-Fi 6), 2.4GHz only |
Bluetooth |
Bluetooth Low Energy (BLE) 5.4 |
Throughput |
Application throughput up to 50 Mbps |
Antenna connector |
IPEX Gen 4 / MHF4 ( |
Certification |
Certified to FCC/CE intentional radiator emission requirements |
Note
5GHz Wi-Fi bands and Bluetooth Classic are not supported by the CC3301. Only the 2.4GHz band and Bluetooth Low Energy are available.
LoRa#
Long-range sub-GHz connectivity is provided by a Seeed Studio
Wio-SX1262 module
(U36), built on the Semtech SX1262 transceiver and connected on SPI3, with a u.FL
antenna connector. It is the hardware behind the Meshtastic support described in
Demos and Tutorials.
One module covers 862 to 930MHz, so the same board serves the EU868 and US915 LoRaWAN plans and the other plans in that range. The region is chosen in software, and the antenna must be tuned to match it.
Important
Transmit only on a band that is permitted where you are, and only with an antenna connected to the u.FL connector.
Both radios: the BM3301-1216 module on SDIO and UART, and the Wio-SX1262 LoRa
module, each with its own power switching and antenna connector.
U25 is the BeagleBoard.org BeagleMod BM3301-1216 (M.2 1216 LGA) built around
the TI CC3301 companion IC: 2.4 GHz Wi-Fi 6 and Bluetooth LE 5.4 with an
MHF4 antenna connector. Wi-Fi uses the AM62L MMC2 SDIO interface
(WIFI_SDIO_*) and BLE uses UART1 with flow control (CC33_UART_*). Interrupts
and reset are on WKUP_GPIO0_2, GPIO0_52 and GPIO0_14. OSC1
(32.768 kHz, DNP) is an optional external slow clock. See Wi-Fi and Bluetooth.
U86 and U87 (TPS22918DBVR, 2 A) create the switched WiFi_3V3 and
WiFi_1V8 rails from VDD_3V3/VDD_1V8. Both are enabled by
AB9/GPIO0_75/1V8 (the WiFi power switch added in v1.0), so the radio can be
completely powered down. The default state is off (“WIFI and BLE close”).
U27 (SN74AXC4T245) translates the 3.3 V UART1 signals from the SoC to the
1.8 V CC33_UART_* lines of the module. DIR pins are fixed so TX/RTS go A→B
and RX/CTS come B→A. OE is tied active.
Optional pull-up/pull-down pairs on BLE_IRQ, WIFI_WL_IRQ and BLE_LOGGER
(mostly DNP). BLE_LOGGER can be pulled to select the module’s debug-log UART mode.
T20/GPIO0_51/WLAN_EN drives WIFI_RST_1V8 through R223. C230/R225
(DNP) allow adding a power-on reset delay if required.
U36 is the Seeed Studio Wio-SX1262 (Semtech SX1262) sub-GHz LoRa module with a
u.FL antenna connector, connected on SPI3 (SPI3_CS0/CLK/D0/D1) with
BUSY/DIO/NRST on GPIO0_41, GPIO0_34 and GPIO0_88/GPIO0_94.
FB7 filters its 3.3 V supply. It covers 862-930 MHz and is the radio behind
Meshtastic. See LoRa.
Display#
4.2 inch ePaper#
The primary display is a 4.2 inch black-and-white electrophoretic (ePaper) module,
HINK-E042A162, with a resolution of 400 x 300 pixels and outline dimensions of
97 x 77 x 1.15mm. It attaches through a 24+2 position, 0.5mm pitch top-contact FPC
connector (FPC0.5K-DH-24AWB).
Because the panel is electrophoretic, it draws current only while the image is changing and holds the last image with no power at all, which is what makes multi-day battery operation on a badge practical.
Todo
Confirm the display controller in the HINK-E042A162 panel against its datasheet.
The Zephyr BeagleBadge board
binds a Solomon Systech SSD1681 driver. Once confirmed, add the full and partial
refresh times.
The 24+2 position FPC connector for the 400 x 300 panel, its SPI interface, the
VGH/VGL boost supply and the optional touch I2C lines.
J9 (FPC0.5K-DH-24AWB, 24+2 position 0.5 mm top-contact) carries the 4-wire SPI
(SPI0_CLK, SPI0_D1 as MOSI, SPI0_CS0, D/C# on SPI0_D0/GPIO0_90),
RES# and BUSY (GPIO0_39) to the 4.2 in 400 × 300 HINK-E042A162 panel,
plus the VSH/VSL/VGH/VGL/VCOM bias caps. See 4.2 inch ePaper.
0 Ω links (DNP) that would connect I2C1 and GPIO0_123 to the panel’s touch
controller pins. For a touch panel of a different model an adapter board is needed.
Use I2C1 as the touch interface.
U71 (SN74LVC1G08) asserts the panel RES# whenever the SoC is in reset or
H20/GPIO0_24 is driven low, so the display controller always starts from a
known state.
The panel controller drives NMOS_GDR to switch Q5 and 47 µH inductor L9, and
the diode/capacitor ladder D45-D47 generates the positive and negative gate
voltages VGH/VGL from EPD_VCC_3V3. R308 (2.2 Ω) is the current-sense
resistor.
BS1 selects the panel interface: R307 fitted (BS1 = 0) gives 4-line SPI
with a separate D/C# pin. R305 fitted (BS1 = 1) selects 3-line SPI.
MIPI DSI#
A 22-position, 0.5mm pitch right-angle FPC connector (130-221-220001-W3G) brings out
the AM62L32 MIPI DSI interface for attaching a conventional LCD panel.
Sensors#
Sensor |
Device |
Notes |
|---|---|---|
6-axis IMU |
ST |
3-axis accelerometer to +/-16g and 3-axis gyroscope to +/-2000 deg/s, LGA-14 |
Ambient light |
Everlight |
Analog phototransistor, conditioned by a |
Temperature and humidity |
Not populated |
Footprint |
Tip
The temperature and humidity sensor is not populated on v1.0. The U40 footprint
takes a Sensirion SHT40 in a 1.5 x
1.5mm DFN package on I2C0, so it can be fitted by hand. The common SHT40-AD1B
answers at I2C address 0x44.
The LSM6DS3TR-C IMU, the ALS-PT19 ambient light sensor with its amplifier,
the RGB LED, the passive buzzer, and the unpopulated temperature/humidity footprint.
U32 (TPS22918) produces the switched Sensor_3V3 rail for the IMU, light
sensor, RGB LED and 7-segment digits. The AND gate U61 enables it from
AA23/WKUP_GPIO0_1 and RESETSTATz so the sensors are off in reset and in
low-power modes.
B1 (MLT-8530H-16R, passive magnetic buzzer) is driven by NPN transistor Q4
from F22/GPIO0_29/PWM, generate a PWM tone in software. D26 clamps the
inductive kick-back. R275 (0 Ω) selects the Sensor_3V3 supply.
D25 (19-237/R6GHBHC-D02/2T, 1.6 × 1.6 mm common-anode RGB LED) is driven by three
N-MOSFETs Q1-Q3 from the PWM-capable GPIO0_83, GPIO0_81 and
GPIO0_82. R276/R277 (1 kΩ) and R278 (2.2 kΩ) set the per-colour current.
U33 (ST LSM6DS3TR-C, 3-axis accelerometer ±16 g + 3-axis gyroscope
±2000 dps) is on I2C0 (IMU_SCL/IMU_SDA through 0 Ω links). INT1 goes to
IMU_INT/3V3 and into the wake-up logic on sheet 22, so motion can wake the badge.
v0.5 added R616/R617 to select the IMU supply between VCC_3V3_MAIN and
VDD_3V3. See Sensors.
Q7 (ALS-PT19-315C, analogue phototransistor) develops a voltage across
R509 (15 kΩ) that op-amp U45 (TLV9061) scales (gain ≈ 1.83) into the
0-1.6 V range of V23/ADC0_AIN2. Maximum output is Vcc − 0.4 V.
Keep C282 next to the AM62L ADC pin.
Footprint U40 for a Sensirion SHT40 temperature and humidity sensor on
I2C0, not populated on v1.0. See Sensors.
User Interface#
Indicators and buzzer#
Device |
Qty |
Part |
|---|---|---|
RGB status LED |
1 |
Everlight |
7-segment digits |
2 |
Built from 14 discrete green 0805 LEDs ( |
Indicator LEDs |
5 |
2 x yellow-green and 3 x clear-blue 0603 |
Passive buzzer |
1 |
|
The two 7-segment digits are driven through a Microchip MCP23S18-E/MJ 16-bit SPI I/O
expander with open-drain outputs, which keeps the segment count off the SoC GPIO banks.
It sits on SPI1 with chip select SPI1_CS0. The mikroBUS socket uses SPI1_CS1.
Expander port |
Segments |
|---|---|
|
Digit 1, segments A to G |
|
Digit 2, segments A to G |
The expander sinks each segment’s cathode, so a segment lights when its bit is driven
low. The digits are powered from Sensor_3V3, which has to be switched on first.
All four push buttons (RESET, power, BACK and the shared SELECT/BOOT button), the
5-way joystick, and the MCP23S18 SPI expander that drives the two 7-segment
digits.
SW2 (6 mm tactile) is the front Select button. The same net,
BOOT/Select/Button/3V3, is also read by the boot-mode logic on sheet 11: holding
it during power-up switches the primary boot from OSPI to SD card. D18 is a
5 V ESD diode. R243 (DNP) is an optional pull-up.
SW3 is the front Back button on D16/GPIO0_104/BACK, pulled up by R244
with D19 ESD protection and C236 debounce capacitor.
SW9 (BLQ-1502-01-06) replaced the four direction buttons in v0.4. Left, Press,
Down, Up and Right map to GPIO0_31, Joystick_Press, GPIO0_42, GPIO0_32
and GPIO0_95. Each line has a 10 kΩ pull-up, 22 pF capacitor and ESD diode. The
press line can also wake the system (sheet 11). See Buttons and joystick.
U42 (MCP23S18-E/MJ, 16-bit SPI I/O expander with open-drain outputs) drives the
fourteen 7-segment LEDs from SPI1 (SPI1_CS0/CLK/D0/D1), keeping them off the SoC
GPIO banks. GPB0-GPB6 are digit 1 segments A-G and GPA0-GPA6 digit 2.
See Indicators and buzzer.
U65 (SN74LVC1G08) resets the expander whenever the SoC is in reset
(RESETSTATz) or software pulls H21/GPIO0_25 low.
The two 7-segment digits are built from 14 discrete green 0805 LEDs
(17-215SYGC/S530-E2/4T), each with a 1 kΩ resistor to Sensor_3V3. The expander
sinks the cathodes, so a segment lights when its bit is driven low.
S1 is the RESET button on the back edge. By default (R271/R641/R642
= 0 Ω, R642 DNP) it drives RESETz for a warm reset. Populating R642
instead routes it to PORz_INPUT for a power-on reset. D24 (ESD0301L) and
the 220 nF C496 were added in v1.0 for ESD robustness.
S2 pulls PMIC_EN to toggle the PMIC and therefore the whole SoC power domain
(added in v1.0). This is the fourth push button the BOM lists. It is on the
VCC_3V3_MAIN domain so it works while everything else is off.
General connectivity and expansion#
USB#
Port |
Description |
|---|---|
USB Type-C |
|
USB 2.0 Type-A host |
|
The USB-C data pair goes to the upstream port of a Texas Instruments TUSB4020BIPHPR
two-port USB 2.0 hub. Downstream port 1 goes to the SoC USB0, so the board appears to
a host PC as a USB device, and downstream port 2 goes to the CP2102N console bridge.
The hub is powered only while USB-C is connected.
The Type-A host port is on the SoC USB1 directly, not behind the hub. Its 5V supply
comes from the on-board boost converter through a TPD3S014 switch that limits it to
500mA and turns it on only when the port is in host mode.
The SoC USB0/USB1 interfaces and the TUSB4020B two-port hub, with its
crystal, configuration straps and unpopulated configuration EEPROM.
Both AM62L USB 2.0 dual-role controllers are used: USB0 connects to the hub’s
upstream port (and therefore the Type-C connector) and USB1 goes straight to the
Type-A host port on sheet 17. R156/R158 (499 Ω, 1 %) are the required
USBx_RCALIB calibration resistors.
U19 (TUSB4020BIPHPR) is a 2-port USB 2.0 hub. Its upstream port is the Type-C
data pair, downstream port 1 goes back to the AM62L USB0 (making the SoC a
device behind the connector) and downstream port 2 feeds the CP2102N
USB-to-UART bridge. GRSTz is driven from M23/GPIO0_43 so software can reset
the hub (v1.0 removed the previous reset supervisor). See USB.
X3 is a 24 MHz, 20 pF crystal with 27 pF load capacitors C180/C181 and 1 MΩ
bias resistor R166 for the hub’s on-chip oscillator.
Pull-up/pull-down networks that set the hub options: PWRCTL_POL,
FULLPWRMGMTZ_SMBA1 and GANGED_SMBA2_HS select individual/ganged power
control and disable the SMBus configuration interface. USB0_VBUS/USB1_VBUS
are derived from TYPEC_5V_IN and USBA_5V so the SoC sees VBUS detection.
Footprint for an FT24C02A SMBus EEPROM that could hold custom hub descriptors.
It is not populated. The hub runs from its default configuration.
FB3/FB4 (120 Ω ferrites) isolate VDD33_USB and VDD_1V1_USB from the LDO
outputs, with one 1 nF/10 nF/100 nF triplet per hub power pin. Place the 0201
capacitors as close to U19 as possible.
The Type-A host receptacle and its power switch, the 5V boost that supplies it, and
the CP2102N bridge that provides the serial console over USB-C.
:annotations: usb-a-port, usb-a-power-switch, boost-5v, boost-enable-gate, usb-uart
J4 (U221-041N-4V33-S5) is a right-angle Type-A receptacle wired directly to
AM62L USB1 through the 90 Ω common-mode choke L7. The shield is tied to
EARTH_USBA through R630/R631. Use it for keyboards, storage and other
peripherals (see USB).
U22 (TPD3S014DBVR) switches BOOST_5V0 to USBA_5V with a 500 mA current
limit and integrated ESD protection for the data lines. It is enabled by
USB1_DRVVBUS from the SoC, so VBUS is only supplied when the port is in host mode.
U23 (LMR62014XMFE) boosts VSYS_OUT (battery or USB) to BOOST_5V0 for the
Type-A port and the mikroBUS 5V pin. R191/R192 (40.2 kΩ / 13.3 kΩ) set
Vout = 1.23 V × (1 + 40.2/13.3) ≈ 4.95 V, up to 600 mA. R188/R189
(DNP) allow bypassing from VDD_3V3 instead.
The AND gate U77 (SN74LVC1G08) enables the boost converter only when
L22/GPIO0_15 is high and the SoC is out of reset (RESETSTATz), so the 5 V
rail never comes up while the SoC is held in reset.
U24 (CP2102N-A02-GQFN24R) hangs off downstream port 2 of the USB hub and
presents the AM62L UART0 console (D13/UART0_RX, C13/UART0_TX) as a virtual
COM port on the same USB-C cable that powers the board. VREGIN is fed from
TYPEC_5V_IN and the internal 3.3 V LDO powers the part. R201 (47 kΩ) is the
VBUS sense divider. See Serial debug.
Two blue 0603 LEDs on TXLED/RXLED of the CP2102N blink with console traffic.
D53 (B5819WS) keeps the LED supply from back-feeding the bridge.
Ecosystem connectors#
Connector |
Qty |
Part |
Description |
|---|---|---|---|
QWIIC |
2 |
|
4-pin, 1.0mm pitch JST-SH style right-angle I2C connectors |
Grove |
1 |
|
4-pin, 2.0mm pitch right-angle connector |
mikroBUS |
1 |
|
A pair of 1x8, 2.54mm pitch vertical female headers |
Pinouts for these connectors are covered in Expansion.
Both QWIIC connectors, the mikroBUS socket with its analog input scaler, and the wake-up logic shared between the IMU and the mikroBUS interrupt line.
J6 (WY-4539, 4-pin 1.0 mm JST-SH style) exposes I2C1 with VDD_3V3 and GND
in the standard QWIIC / STEMMA QT pin order. FB8-FB11 and D27/D28
provide EMI filtering and ESD protection. I2C1 is shared with the mikroBUS socket
and the DSI connector. See Ecosystem connectors.
J7 is the second QWIIC connector, on its own bus I2C2 so that modules with
fixed addresses can be used on both connectors at once.
Op-amp U38 (TLV9061) with R312/R313 scales the mikroBUS AN pin
(0-3.3 V) down to 0-1.72 V for V22/ADC0_AIN1, protecting the 1.8 V ADC input.
U79 (open-drain buffer) and U84 (AND gate) combine Mikrobus_INT and
IMU_INT into EXT_WAKEUP1/1V8 on the SoC wake-up domain: either interrupt
going low wakes the AM62L from deep sleep. U85 (DNP) is an alternative
inverting path.
J20/J21 (two 1×8 2.54 mm headers) form the mikroBUS socket: AN (scaled to
ADC0_AIN1), RST/CS/SCK/MISO/MOSI on SPI1 (shared with the
7-segment expander), PWM on GPIO0_33, INT on GPIO0_44, RX/TX on
UART5 and SCL/SDA on I2C1. 5V comes from the boost converter through
D48, limited to 0.1 A. Every pin has a TPD1E10B04 ESD diode.
GPIO expansion header#
J28 and J27 are two 15-pin headers, not fitted with connectors, that bring out
both RGMII ports, the MDIO0 pair, ADC0_AIN3 and the 1.8V and Sensor_3V3
supplies. With no Ethernet PHY on the board, every RGMII pin is available as 1.8V GPIO.
The pinout is in GPIO expansion header.
Sheet 24 carries three blocks: the two GPIO expansion headers, the Grove connector
(wired as an I2C1 port at 3.3V), and the 22-pin FPC connector for a MIPI DSI
panel described in MIPI DSI.
J27, the right-hand of the two 15-pin headers below the lanyard slot, not fitted
with a connector. It carries RGMII2 and the MDIO0 pair as 1.8 V GPIO, with
Sensor_3V3 on pin 1 and ground on pin 15. See GPIO expansion header.
J28, the left-hand of the two 15-pin headers below the lanyard slot, not fitted
with a connector. It carries the 1.8 V supply on pin 1, RGMII1 as 1.8 V GPIO,
ADC0_AIN3 on pin 14 and ground on pin 15. See GPIO expansion header.
J25, a 4-pin 2.0 mm right-angle Grove socket wired as an I2C port on I2C1
(I2C1_SCL / I2C1_SDA, 3.3 V), shared with QWIIC connector 1 and the mikroBUS
socket. Pin 3 is VDD_3V3 and pin 4 is ground, so Grove modules that expect a 5 V
supply will not work here without a supply adapter. R626 is a DNP option on the
bus. See Grove connector.
J24 (FPC 22P 0.5mm, part 130-221-220001-W3G) carries the four MIPI DSI data
lanes and the clock pair from sheet 15 to an LCD panel, with a ground between each pair,
I2C1 for a touch controller, and VDD_3V3. Q9 and Q10 (BSS138W) shift
WKUP_GPIO0_3 and WKUP_GPIO0_0 from 1.8 V to 3.3 V for pins 17 and 18. The layout
note asks for C379 to be placed close to the SoC. See FPC connectors.
Debug Ports#
Serial debug#
A Silicon Labs CP2102N-A02-GQFN24R USB-to-UART bridge is fitted on-board and shares
the USB Type-C connector, so a single cable carries power and the console with no debug
probe required. The console is presented on the SoC main_uart0 interface.
Port settings and host device names are in Serial console.
JTAG#
The board exposes JTAG on an edge SOICbite connector, which allows a standard SOIC test clip to be used for hardware-level debugging without fitting a dedicated header.
Todo
Add the J29 pinout table from schematic sheet 19.
The SoC JTAG pins, the 1.8V to 3.3V buffer added in revision V0.7, the SOIC16 SOICbite debug footprint and the 32Kbit board-identity EEPROM.
The AM62L TDO/TDI/TMS/TCK/TRSTn pins live in the 1.8 V VDDS0
domain with 10 kΩ pull-ups (R233-R237). EMU0/EMU1 are brought to test
points TP27/TP28. See JTAG.
U80 (SN74AXC4T245) translates TDI, TCK, TMS and TRST# from the
3.3 V SOICbite side to the 1.8 V SoC side (v0.7 change: JTAG signals to 3.3 V through
a buffer). R633-R636 (DNP, bottom of sheet) can bypass the shifter.
U81 (SN74LV1T125) buffers SoC_TDO/1V8 out to 3.3 V for the debug probe.
J29 is a SOICbite footprint: a SOIC-16 land pattern that accepts a standard test
clip instead of a dedicated header. Pins 1-8 carry JTAG and RESETz, pins 9-15 bring
out the Back/Select/joystick button lines and EXT_WAKEUP0, pin 16 is GND (the
full pin list is printed on the sheet). U78 buffers EXT_WAKEUP0 into the 1.8 V
wake-up domain. See JTAG.
U35 (FT24C32A-ELRT, 32 Kbit I2C EEPROM, SOT23-5) on I2C0 holds the board
identity written at manufacturing, following the BeagleBoard.org convention. WP
is pulled up by R241. pull ``TP16`` low to write the EEPROM.
See Storage.
Mechanical specifications#
Dimensions and weight#
Parameter |
Value |
|---|---|
Board size |
110 x 91 mm |
PCB layers |
6 layers |
PCB thickness |
1.6 mm |
PCB colour |
Black |
ePaper module |
97 x 77 x 1.15 mm |
Mounting |
4 x M2 bronze standoffs ( |
Gross weight |
|
Net weight |
The 6-layer stackup is, from top to bottom: L1_TOP, L2_GND1, L3_SIG1,
L4_SIG2, L5_PWR, L6_BOTTOM.
Todo
Add a dimensioned drawing and the top and bottom silkscreen images, exported from the board files in the BeagleBadge repository, and the measured board weight.